1. Field of the Invention
The present invention relates to circuit verification and more particularly to verification of a register in a circuit.
2. Description of the Related Art
Conventionally, when hardware (a circuit) is designed to implement a desired function, work to execute logic verification to check for oversights in the contents of the design is necessary prior to proceeding to the actual hardware fabrication. More specifically, a verification scenario in line with the contents of the design of the hardware is created and logic verification is executed using the output result obtained when the verification scenario is input. For an example, refer to the convention art disclosed in Japanese Patent Application Laid-Open Publication No. 2006-190209.
However, parameter settings of a verification scenario used for conventional logic verification have many deficiencies arising in a problem of low verification efficiency. For example, one approach involves executing a verification scenario into which a randomly designated parameter is substituted. However, this approach can not cover all the verification examples and, therefore, verification oversights may occur.
Further, another approach proposes designating the maximal value, the minimal value, and a typical value among the values that can be as the parameters. However, the path that was originally intended to be verified may not be included the verification. In both of the approaches above, the use and the range of a value to be designated as a parameter is defined according to the specification of the hardware design. Therefore, the verification scenario is not a verification scenario for which a parameter is set to cover a specific register in the hardware. Therefore, the verification efficiency cannot be improved.
When hardware is designed based on specifications, a register that is not specified in the specifications may be disposed according to the configuration for implementation. No parameter for the verification scenario is considered for the implementation-dependent register that is used only for the implementation as above. Therefore, no verification that covers the case where the implementation-dependent register is present in the designed hardware is executed, a factor that reduces verification efficiency.